Perancangan Algoritma Rsa Crt Menggunakan Vhdl

Kusumawardhana, Adhitya (2020) Perancangan Algoritma Rsa Crt Menggunakan Vhdl. Other thesis, Universitas Komputer Indonesia.

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Abstract

Pada penelitian ini dilakukan perancangan perangkat keras algoritma RSA CRT yang diimplementasikan pada Field Programmable Gate Array (FPGA). Pada perancangannya diutamakan operasi perhitungan paralel sehingga mencapai speed optimum. Spesifikasi algoritma yang digunakan dalam perancangan adalah spesifikasi Algoritma RSA CRT yang telah diimplementasikan pada perangkat lunak, diantaranya masukan dan keluaran blok data adalah 128 bit dengan lebar kunci 128 bit. Perancangan dilakukan dengan menggunakan Very High Speed Integrated Circuit (VHSIC) High Description Language (VHDL). Simulasi dilakukan menggunakan ModelSim 10.1d dan diimplementasi pada Development Board DE2 Altera Cyclone II Tipe EP2C35F672C7.

Item Type:	Thesis (Other)
Uncontrolled Keywords:	algoritma RSA CRT, implementasi perangkat keras, FPGA
Subjects:	000_COMPUTER SCIENCE, INFORMATION & GENERAL WORKS. > 004_Data Processing & Computer Science
Divisions:	S1_SKRIPSI > FTIK_Sistem Komputer (02)
Depositing User:	Mrs. Calis Maryani
Date Deposited:	05 Nov 2020 04:16
Last Modified:	05 Nov 2020 04:16
URI:	http://elibrary.unikom.ac.id/id/eprint/2768

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